Hello I am asking here because I do not see a general firmware Stack Exchange or better place. I am open to suggestions on that.

But my question is pertaining to Intel Atom SoCs. I am interested in when the processor resets, then the BSD executes instructions from 0xFFFFFFF0 which is 16 bytes below the 1 MB limit in real mode. What should my firmware do at this point, I think it should perform a jump to somewhere that the BIOS/firmware is mapped to. Basically can someone map out the 16 MB Spi flash ROM to logical addresses on the SoC.

  • 3
    Hello and welcome! I am not sure if this is / should be on-topic here. Maybe electronics.stackexchange.com is a better fit.
    – Ghanima
    Jan 4, 2017 at 22:29
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    Welcome to the IoT.SE. I checked briefly with the EE guys and it might be on-topic there. You might want to provide a bit more information though, because the question didn't seem too clear. Meanwhile we can discuss on Internet of Things Meta if we consider questions like this on-topic here.
    – Helmar
    Jan 4, 2017 at 23:20
  • For the time being I would like you to elaborate a bit more, what exactly you want to know, the question is a bit unclear to me.
    – Helmar
    Jan 4, 2017 at 23:26
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    Related meta discussion: meta.iot.stackexchange.com/q/178/54
    – Ghanima
    Jan 4, 2017 at 23:32
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    See here: superuser.com/questions/988473/…
    – ceving
    Jan 3, 2018 at 14:51

1 Answer 1


The firmware should jump to a routine that reads the second stage boot loader into RAM and then execute it. To map the SPI in the logical memory space the SoC would have to support this internally.

The question is not out of place here, but you can always ask hardware related questions at Electrical Engineering.SE.

  • Thanks I haven't been at home long enough to ask at electronics. Seems to me a general firmware or even a x86 and ARM firmware's stack exchange would be nice. The NVRAM is not yet available. The SPIis mapped as the first instruction is at code segment 16 bytes below the the 1 Mbyte limit in real mode from the cpu's perspective. That first opcode byte is a location on the SPI flash. My problem is I do not know where it should be. At this point I am beginning to believe it is different for different intel cpu. Jan 6, 2017 at 6:50
  • I have read for atom e3800 that it should be right after the 4kbyte block so spi flash address 0xF9F plus one. I have read else where that it should be the last address of the supported flash size in non descriptor mode. In any case does somebody know the one to one map of a processor address to the spi flash? Maybe I will try asking on intel forum. Also I'm aware some stuff is confidential but also some stuff has been released from it's confidentiality or is readily observable on spi flash so maybe somebody knows. If I find out and am not under nda I will answer the question as it help others Jan 6, 2017 at 7:00

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